The present disclosure relates to semiconductor manufacturing, and more particularly to methods for detecting a layout of an integrated circuit located upon a semiconductor substrate.
Integrated circuit (IC) layout is the representation of an IC in terms of planar geometric shapes which correspond to patterns of semiconductor material, insulator material and/or conductive material that constitute the IC. For many applications, it is necessary to detect the actual physical circuit layout on a semiconductor chip. For various applications, the level of detection may vary. However, there are specific applications whereby the comparison of the actual layout to the corresponding design layout is essential for verification of the integration process.
The majority of the conventional techniques use back-polishing semiconductor wafers down to a tens or microns in conjugation with extremely high energy beam imaging, or electron back-scattering techniques to detect the physical layout of the semiconductor chip. Nonetheless, none of the prior art techniques provide enough resolution for discerning various layers/components of the semiconductor chip. As such, alternative techniques are needed that can be used to detect a layout of an IC.